1. Field
Embodiments of the present invention generally relate to methods for forming silicon recess structures in a semiconductor substrate, and more particularly to methods for forming silicon recess structures in a semiconductor substrate utilizing a doping layer implanted by an ion implantation process as an etching stop layer for fin field effect transistor (FinFET) semiconductor manufacturing applications.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
A patterned mask, such as a photoresist layer or a hardmask layer, is commonly used in forming structures, such as gate structure, shallow trench isolation (STI), bite lines and the like, on a substrate by etching process. The patterned mask is conventionally fabricated by using a lithographic process to optically transfer a pattern having the desired critical dimensions to a layer of photoresist or a hardmask layer. For example, the photoresist layer is then developed to remove undesired portion of the photoresist, thereby creating openings in the remaining photoresist. In the case an additional hardmask layer is utilized, the hardmask layer can then further be etched/patterned using openings formed in the remaining photoresist as an etching mask.
In order to enable fabrication of next generation devices and structures, three dimensional (3D) stacking of semiconductor chips is often utilized to improve performance of the transistors. In particular, fin field effect transistors (FinFET) are often utilized to form three dimensional (3D) stacking of semiconductor chips. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other.
FIG. 1A depicts an exemplary embodiment of a fin field effect transistor (FinFET) 150 disposed on a substrate 100. The substrate 100 may be a silicon substrate, a germanium substrate, or a substrate formed from other semiconductor materials. In one embodiment, the substrate 100 may include p-type or n-type dopants doped therein. The substrate 100 includes a plurality of semiconductor fins 102 formed thereon isolated by shallow trench isolation (STI) structures 104. The shallow trench isolation (STI) structures 104 may be formed by an insulating material, such as a silicon oxide material.
The substrate 100 may includes a portion in NMOS device region 101 and a portion in PMOS device region 103, and each of the semiconductor fins 102 may be sequentially and alternatively formed in the NMOS device region 101 and the PMOS device region 103 in the substrate 100. The semiconductor fins 102, 152 are formed above the top surfaces of the shallow trench isolation (STI) structures 104. Subsequently, a gate structure 106, typically including a gate electrode layer disposed on a gate dielectric layer, is deposited on both of the NMOS device region 101 and the PMOS device region 103 and over the semiconductor fins 102, 152.
The gate structure 106 may be patterned to expose portions 148, 168 of the semiconductor fins 102, 152 uncovered by the gate structure 106. The exposed portions 148, 168 of the semiconductor fins 102 may then be doped with dopants to form pocket and lightly doped source and drain (LDD) regions by an implantation process.
FIG. 1B depicts a cross sectional view of the substrate 100 including the plurality of semiconductor fins 102 formed on the substrate 100 isolated by the shallow trench isolation (STI) structures 104. The plurality semiconductor fins 102 formed on the substrate 100 may be part of the substrate 100 extending upwards from the substrate 100 utilizing the shallow trench isolation (STI) structures 104 to isolate each of the semiconductor fins 102. In another embodiment, the semiconductor fins 102 may be individually formed structures disposed on the substrate 100 that are made from materials different than the substrate 100 using suitable techniques in the art. In the embodiment wherein semiconductor fins 102 is not the part of the substrate 100, silicon recess structures 160, as shown in FIG. 1C, are required to be formed in the substrate 100 and isolated by the shallow trench isolation (STI) structures 104. The silicon recess structures 160 formed in the substrate 100 may then be filled with different materials, such as SiGe containing material, Ge containing material, Group III-V materials, or other compound materials, to form the structures of the semiconductor fins 102.
However, as the designs of the three dimensional (3D) stacking of fin field effect transistor (FinFET) 150 are pushed up against the technology limits for the structure geometry, the need for accurate process control for the manufacture of small critical dimension silicon recess structures 160 in the substrate 100 has become increasingly important. Conventional processes for forming silicon recess structures often suffer from low selectivity, poor profile control and pattern loading effect, thereby resulting in inaccurate silicon recess structure profiles and poor dimension control. For example, a bottom surface 162 (e.g., a front end) of the silicon recess structures 160 is often desired to be maintained flat and/or sharp to as to provide a good interface for the semiconductor fins 102 with different materials to be formed thereon. Furthermore, in the substrate where the silicon recess structures 160 are formed therein with different pattern densities, different etching rates caused by the micro-loading effect often result in profile mismatched or bottom surface roughness due to overetching (or underetching), thereby adversely creating poor profile control over the silicon recess structures 160 after manufacturing process.
Thus, there is a need for improved methods for forming silicon recess structures in a substrate with good profile and dimension control for three dimensional (3D) stacking of semiconductor chips or other semiconductor devices.